1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an auto-refresh control circuit for a semiconductor device.
2. Description of the Related Art
Generally, the auto-refresh operation of a synchronous memory is very similar to a CBR (CAS-Before-RAS) refresh operation of an asynchronous memory. Namely, in the auto-refresh operation of the synchronous memory, a row address counter is operated whenever an auto-refresh command signal is inputted thereinto, and the signals are sequentially refreshed without using an externally inputted address signal. At this time, a minimum period of the auto-refresh cycle is previously set. Therefore, the circuit is configured so that the auto-refresh operation is performed within a previously set time.
In addition, during the semiconductor fabrication process, a burn-in test, namely, a high temperature and high voltage acceleration operation test, is performed in order to check for a defective product. During the burn-in test, an auto-refresh time is generally used.
The auto-refresh control circuit which is used during the burn-in test needs a control by which an extended memory array activation is made possible for a more effective control and test time saving unlike the operation in the normal mode.
FIG. 1 illustrates a conventional auto-refresh control circuit. Referring to FIG. 1, the conventional auto-refresh control circuit includes a synchronous buffer 10 for outputting a synchronous signal by synchronizing an externally inputted command signal RASB to a clock signal CLK, a burn-in signal generator 20 for detecting a burn-in test state and generating a burn-in signal BI, an auto-refresh command signal decoder 30 for receiving and decoding command signals sCSB, sRASB, sCASB, and sWET which are synchronized by a clock signal, and a refresh control signal generator 40 enabled by a burn-in signal BI from the burn-in signal generator 20, for generating a refresh control signal REFC in accordance with a refresh signal REF from the command signal decoder 30.
As shown in FIG. 2, the synchronous buffer 10 includes inverters I1 and I2, connected in series to each other, for sequentially delaying externally inputted command signals RASB, and a synchronous signal generator 11 for outputting a synchronous signal sRAS by synchronizing the command signal RASB, which are inputted thereinto through the inverters I1 and I2, to the clock signal.
As shown in FIG. 3, the burn-in signal generator 20 includes NMOS transistors T1 through T4 connected in series to a voltage V.sub.DD, an NMOS transistor T5 having a gate connected to the power voltage V.sub.DD, the source connected to a ground voltage V.sub.SS, and the drain connected to the drain of the fourth NMOS transistor T4. Inverters I3 and I4 sequentially delay the signals from the node F to which the drain of the NMOS transistor T5 is connected. Here, the NMOS transistors T1 through T4 which are connected in series to the voltage V.sub.DD receive source inputs through the gate of the same.
In the burn-in signal generator 20, the number of NMOS transistors T1 through T4 are subject to the level of the voltage to be set. If a voltage higher than the set voltage level is applied, the NMOS transistors T1 through T4 are turned on, and the node F becomes a high level, so that the burn-in signals BI are outputted through the inverters I3 and I4.
As shown in FIG. 4, the command signal decoder 30 includes an NAND-gate N1 which receives four command signals sCSB, sRASB, sCASB, and sWET which are synchronized by the clock signal.
As shown in FIG. 4, the refresh control signal generator 40 includes a pulse generator 41 for generating pulses in accordance with a signal from the command signal decoder 30. A normal pulse expander 42 and burn-in pulse expander 43 expand the pulse signal from the pulse generator 41 in accordance with a burn-in signal BI from the burn-in signal generator 20. A control signal output unit 44 receives the signals from the normal pulse expander 41 and burn-in pulse expander 43 and outputs a refresh control signal.
The pulse generator 41 includes three inverters I5 through I7 which are connected in series for sequentially delaying and inverting the output signals from the command signal decoder 30, and a NOR-gate O1 for "NORing" (performing a logical NOR operation) the delayed and inverted signal from the inverters I5 through I7 and the output signal from the command signal decoder 30.
The normal pulse expander 42 includes a delay unit D1, which is enabled by the output from the inverter I8 for inverting the burn-in signal BI from the burn-in signal generator 20 and delaying the output from the pulse generator 41, and a NOR-gate O2 for NORing the output from the delay unit D1 and the output from the pulse generator 41.
The burn-in expander 43 includes a delay unit D2, which is enabled by the burn-in signal BI from the burn-in signal generator 20, for delaying the output from the pulse generator 41, and a NOR-gate O3 for NORing the output from the delay unit D2 and the output from the pulse generator 41.
The control signal output unit 44 includes a NAND-gate N2 for performing a "NANDing" (performing a logical NAND operation) operation in accordance with the outputs from the normal pulse expander 42 and the burn-in pulse expander 43, and outputting a refresh control signal REFC.
The operation of the conventional auto-refresh control circuit for a semiconductor device will now be explained with reference to the accompanying drawings.
Referring to FIGS. 5A-5E, when the refresh command signals sCSB, sRASB, sCASB and sWET (where "s" means synchronous, "B" means bar, and "T" means true), which are synchronized by the external clock signal CLK (FIG. 5A) are inputted into the NAND-gate N1 of the refresh command signal decoder 30, node A becomes a low level. The pulse generator 41, which receives the signal from the node A, generates pulses and transmits the same to node B.
When the burn-in signal BI from the burn-in signal generator 20 is at a low level, the output node D of the burn-in pulse expander 43 becomes a high level, and the signal from the output node C of the normal pulse expander 42 is inverted by the NAND-gate N2 as an auto-refresh control signal REFC.
At this time, the pulse expansion by the normal pulse expander 42 as shown in FIG. 5D is determined by the delay unit D1 such that the minimum standard period of the auto-refresh cycle is satisfied.
In addition, when the burn-in signal from the burn-in signal generator 20 is at a high level, the output node C of the normal pulse expander 43 becomes a high level, and the signal from the output node D of the burn-in pulse expander 43 is inverted by the NAND-gate N2 as a control signal REFC.
The pulse expansion by the burn-in pulse expander 43, as shown in FIG. 5E, is determined by the delay unit D2 based on the efficiency of the burn-in test.
Here, when the burn-in signal BI from the burn-in signal generator 20 is at a low level, the circuit is in the normal operation state, not in the burn-in state. In addition, when the burn-in signal BI is at a high level, the circuit is in the burn-in state.
As shown in FIGS. 5D and 5E, the auto-refresh control signal REFC (burn-in) is configured to have a pulse width that is greater than (a few or tens of times) the width of the pulse in the normal operation state, so that the memory array activation is extended, the burn-in test time can be shortened, and the construction of the test apparatus is simplified.
However, in the conventional auto-refresh control circuit, since the pulse width of the auto-refresh control signal REFC is fixed during the burn-in test, it is impossible to control the REFC signal. Therefore, it is impossible to effectively perform the burn-in test. Moreover, to generate a lengthy pulse, the area of the chip layout must be undesirably increased.